MAIR_EL1, Memory Attribute Indirection Register (EL1)

Provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations at EL1.

Contains 8x Attr fields. Each is 8 bits.

 64   56                       7     0
| Attr7 | Attr6 | Attr5 | ... | Attr0 |

>>>> Following are all in binary encoding <<<

Attr                meaning
---------------------------------
0b0000dd00          Device Memory
0booooiiii          Normal memory 
    oooo != 0000
    iiii != 0000

Following are NaN if FEAT_XS not implemented
0000dd01    Device Memory w. XS set to 0
10000000    Normal, Inner NC, Outer NC
10100000    Normal, Inner WT+C, Outer WT+C, RA, NWA, NT with XS=0
11110000    Normal, Tagged, Inner WB, Outer WB, RA, WA, NT;


dd                  meaning
---------------------------------
00                  Device-nGnRnE
01                  Device-nGnRE
10                  Device-nGRE
11                  Device-GRE

oooo                meaning
---------------------------------
0000                See Attr encoding
00RW (RW not 00)    Normal memory, outer write-through transient
0100                Normal memory, outer non-cacheable
01RW (RW not 00)    Normal memory, outer write-back transient
10RW                Normal memory, outer write-through non-transient
11RW                Normal memory, outer write-back non-transient


iiii        Meaning: Same for oooo, but "Inner"
-----------------------------------------------

R or W      Meaning (Read-Allocate / Write-Allocate policy)
-----------------------------------------------
0           No Allocate
1           Allocate

Misc:

(N)C        : Non-Cacheable
WA/WT/WB    : Write Allocate/Write Through/Write Back
NT          : Non-transient