(WIP)

TLB instructions

Invalidate TLB entries

TLBI  <type><level>{IS} {,<Xt>}

The following code example shows a sequence for writes to translation tables backed by inner shareable memory:

<< Writes to Translation Tables >>
DSB ISHST   // ensure write has completed
TLBI ALLE1  // invalidate all TLB entries
DSB ISH     // ensure completion of TLB invalidation
ISB         // synchronize context and ensure that no instructions are
            // fetched using the old translation

For a change to a single entry, for example, use the instruction:

TLBI VAE1, X0

which invalidates an entry associated with the address specified in the register X0.