ESR Decoder: https://esr.arm64.dev/
Aarch64 translation fault related stuffs.
ESR_EL1
/// TODO ADD ESR_EL1
ESR.EC
- 0x20 - instr abort low
- 0x21 - instr abort current
- 0x24 - data abort low
- 0x25 - data abort current
/// TODO ADD OTHER ECs /// TODO ADD DFSC AND IFSC
ESR.ISS for instr abort
BIT [xx:xx] .
BIT [24] ISV Instruction Syndrome Valid
- Following bits are only valid when isv=1
BITS[23:22] SAS Syndrome Access Size
- 0b00 : 1 x byte
- 0b01 : 2 x byte
- 0b10 : 3 x byte
- 0b11 : 4 x byte
BIT [21] SSE Syndrome Sign Extend
- 0b0 Sign ext not required
- 0b1 sign ext required
BITS[20:16] SRT Syndrome Register Transfer
- register number of Xt/Xt/Rt operands of faulting instr
BIT [15] SF Sixty Four bit general-purpsoe register transfer
- 0b0 instr loads/stores 32-bit GPR
- 0b1 instr loads/stores 64-bit GPR
BIT [14] AR Acquire/Release
BIT [13] VNCR indicates fault came from VNCR_EL2 in EL1 code
BITS[12:11] SET Synchronous Error Type
- When FEAT_RAS is implemented and DFSC == 0b010000
BITS[12:11] LST Load/Store Type
- When FEAT_LS64 is implemented and DFSC == 0b110101
BIT [10] FnV FAR not valid
- 0 FAR is valid
- 1 FAR not valid, value unknown
BIT [9] EA
BIT [8] CM
BIT [7] S1PTW
- 0 Fault NOT on stage 2
- 1 Fault on stage 2
BIT [6] WnR
BITs[5:0] DFSC Data Fault Status Code
ESR.ISS for data abort
BITs[24:13] RES0
BITS[12:11] SET Synchronous Error Type
- When FEAT_RAS is implemented and IFSC == 0b010000
BITS[12:11] LST Load/Store Type
- When FEAT_LS64 is implemented and IFSC == 0b110101
BIT [10] FnV FAR not valid
BIT [9] EA
BIT [8] RES0
BIT [7] S1PTW
BIT [6] RES0
BITs[5:0] IFSC Data Fault Status Code
ESR.ISS.IFSC / DFSC See the documents, it sucks.
PARTIALLY:
// Access Size Fault L0~3
DFSC_ASF_L0 = 0x0;
DFSC_ASF_L1 = 0x1;
DFSC_ASF_L2 = 0x2;
DFSC_ASF_L3 = 0x3;
// Translation Fault L0~3
DFSC_TF_L0 = 0x4;
DFSC_TF_L1 = 0x5;
DFSC_TF_L2 = 0x6;
DFSC_TF_L3 = 0x7;
// Access Flag Fault L0~3
DFSC_AF_L0 = 0x8; /* if FEAT_LPA2 is implmented */
DFSC_AF_L1 = 0x9;
DFSC_AF_L2 = 0xa;
DFSC_AF_L3 = 0xb;
// Permission Fault L0 ~ 3
DFSC_PF_L0 = 0xc; /* if FEAT_LPA2 is implemented */
DFSC_PF_L1 = 0xd;
DFSC_PF_L2 = 0xe;
DFSC_PF_L3 = 0xf;
// Synchronous External Abort (SEA)
// not on translation table walk
DFSC_SEA = 0x10;
// on translation table walk, L -1~3
DFSC_SEA_M1 = 0x13; /* if FEAT_LPA2 is implemented*/
DFSC_SEA_L0 = 0x14;
DFSC_SEA_L1 = 0x15;
DFSC_SEA_L2 = 0x16;
DFSC_SEA_L3 = 0x17;
// Synchronous parity or ECC error when FEAT_RAS NOT implemented.
// not on table walk
DFSC_ECC = 0x18;
// on table walk: L-1~3
DFSC_ECC_M1 = 0x1b;
DFSC_ECC_L0 = 0x1c;
DFSC_ECC_L1 = 0x1d;
DFSC_ECC_L2 = 0x1e;
DFSC_ECC_L3 = 0x1f;
pub const DFSC_ALIGN:u64 = 0x21;
// the Granule Protection Faults
// GPF on table walk, L-1~3
DFSC_GPF_M1 = 0x23;
DFSC_GPF_L0 = 0x23;
DFSC_GPF_L1 = 0x25;
DFSC_GPF_L2 = 0x26;
DFSC_GPF_L3 = 0x27;
// GPF not on table walk
pub const DFSC_GPF = 0x28;
DFSC_ASF_M1 = 0x29;
DFSC_TF_M1 = 0x2b;
DFSC_TLB_CONFLICT = 0x30;
// unsupported atomic hardware update
DFSC_UAHU = 0x31;
https://developer.arm.com/documentation/ddi0595/2021-12/AArch64-Registers/ESR-EL1--Exception-Syndrome-Register--EL1-?lang=en#fieldset_0-24_0_13