AT instr: test address translation from VA.
AT S<m>E<n><R/W><P>, <Xt>
<m> translation stage
<n> Exception Level
<R/W> R or W, for Read / Write
<P> OPTIONAL: test with PAN when implemented
<Xt> Holds virtual address
PAR_EL1 Holds result
MRS <Xt>, PAR_EL1
PAR_EL1[63:0]
[63:56] ATTR: Memory Attr, same as in MAIR_EL1
[55:52] RES0
[51:48] PA[51:48] <OPT> / RES0
[47:12] PA[47:12]
[11 ] NSE <OPT> / RES1
[10 ] impl. defined
[9 ] NS (Non Secure)
[8 : 7] SH
[6 : 1] RES0
[0 ] F (1==failure)
Memory Attr Encoding: also see this for details.
It's a 8 bits value:
Value Meaning
---------------------------------
0000dd00 Device Memory
0000dd1x NaN
ooooiiii Normal Memory (oooo!=0000, iiii!=0000)
dd Meaning
---------------------------------
00 Device nGnRnE
01 Device nGnRE
10 Device nGRE
11 Device GRE
oooo Meaning: (Outer)
---------------------------------
0000 NaN
00RW Normal Memory, outer WT Transient (RW!=00)
0100 Normal Memory, outer NC
01RW Normal Memory, outer WB Transient (RW!=00)
10RW Normal Memory, outer WT, NT
11RW Normal Memory, Outer WB, NT
iiii Meaning: Same for oooo, but "Inner"
-----------------------------------------------
R or W Meaning (Read-Allocate / Write-Allocate policy)
-----------------------------------------------
0 No Allocate
1 Allocate
SH[1:0]
00 Non Shareable
10 Outer Shareable
11 Inner Shareable
NS/NSE
// TODO
NSE NS Meaning
------------------------
0 0 Res*
0 1 Non-Secure
1 0 Root
1 1 Realm
* if secure state is implemented: Secure. Otherwise reserved.
This is obsoleted by Realm